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<div class="header">
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<a href="#pub-attribs">Data Fields</a>  </div>
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<div class="title">GICInterface_Type Struct Reference<div class="ingroups"><a class="el" href="group__GIC__functions.html">Generic Interrupt Controller Functions</a></div></div>  </div>
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<p>Structure type to access the Generic Interrupt Controller Interface (GICC)  
</p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-attribs"></a>
Data Fields</h2></td></tr>
<tr class="memitem:a5969edab40aa24e4d96e072af187a3a9"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a></td></tr>
<tr class="memdesc:a5969edab40aa24e4d96e072af187a3a9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x000 (R/W) CPU Interface Control Register.  <a href="#a5969edab40aa24e4d96e072af187a3a9">More...</a><br/></td></tr>
<tr class="separator:a5969edab40aa24e4d96e072af187a3a9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b">PMR</a></td></tr>
<tr class="memdesc:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x004 (R/W) Interrupt Priority Mask Register.  <a href="#a0edadabc6e3ce1f36d820f0b52bc143b">More...</a><br/></td></tr>
<tr class="separator:a0edadabc6e3ce1f36d820f0b52bc143b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a949317484547dc1db89c9f7ab40d1829"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">BPR</a></td></tr>
<tr class="memdesc:a949317484547dc1db89c9f7ab40d1829"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x008 (R/W) Binary Point Register.  <a href="#a949317484547dc1db89c9f7ab40d1829">More...</a><br/></td></tr>
<tr class="separator:a949317484547dc1db89c9f7ab40d1829"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aa48569605fc0c163e1db35321b4c76ea"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">IAR</a></td></tr>
<tr class="memdesc:aa48569605fc0c163e1db35321b4c76ea"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x00C (R/ ) Interrupt Acknowledge Register.  <a href="#aa48569605fc0c163e1db35321b4c76ea">More...</a><br/></td></tr>
<tr class="separator:aa48569605fc0c163e1db35321b4c76ea"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4b9baa43aae026438bad64e63df17cdb"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">EOIR</a></td></tr>
<tr class="memdesc:a4b9baa43aae026438bad64e63df17cdb"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x010 ( /W) End Of Interrupt Register.  <a href="#a4b9baa43aae026438bad64e63df17cdb">More...</a><br/></td></tr>
<tr class="separator:a4b9baa43aae026438bad64e63df17cdb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a37762d42768ecb3d1302f34abc7f2821"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821">RPR</a></td></tr>
<tr class="memdesc:a37762d42768ecb3d1302f34abc7f2821"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x014 (R/ ) Running Priority Register.  <a href="#a37762d42768ecb3d1302f34abc7f2821">More...</a><br/></td></tr>
<tr class="separator:a37762d42768ecb3d1302f34abc7f2821"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:af793cd280a74bf73cca8c4fedfc329d6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">HPPIR</a></td></tr>
<tr class="memdesc:af793cd280a74bf73cca8c4fedfc329d6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register.  <a href="#af793cd280a74bf73cca8c4fedfc329d6">More...</a><br/></td></tr>
<tr class="separator:af793cd280a74bf73cca8c4fedfc329d6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">ABPR</a></td></tr>
<tr class="memdesc:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x01C (R/W) Aliased Binary Point Register.  <a href="#a6d3ca9eaae5e0ac38f20846a1e67180d">More...</a><br/></td></tr>
<tr class="separator:a6d3ca9eaae5e0ac38f20846a1e67180d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">AIAR</a></td></tr>
<tr class="memdesc:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x020 (R/ ) Aliased Interrupt Acknowledge Register.  <a href="#a849e9ead6e9ced78dc6f0ba9256dd5a6">More...</a><br/></td></tr>
<tr class="separator:a849e9ead6e9ced78dc6f0ba9256dd5a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">AEOIR</a></td></tr>
<tr class="memdesc:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x024 ( /W) Aliased End Of Interrupt Register.  <a href="#a89d5a920c2b91b4b7bd0312ba4c38a89">More...</a><br/></td></tr>
<tr class="separator:a89d5a920c2b91b4b7bd0312ba4c38a89"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a12f25dec95ab3dd13a477573fab4b9c8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">AHPPIR</a></td></tr>
<tr class="memdesc:a12f25dec95ab3dd13a477573fab4b9c8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x028 (R/ ) Aliased Highest Priority Pending Interrupt Register.  <a href="#a12f25dec95ab3dd13a477573fab4b9c8">More...</a><br/></td></tr>
<tr class="separator:a12f25dec95ab3dd13a477573fab4b9c8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abd978b408fb69b7887be2c422f48ce7e"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e">STATUSR</a></td></tr>
<tr class="memdesc:abd978b408fb69b7887be2c422f48ce7e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x02C (R/W) Error Reporting Status Register, optional.  <a href="#abd978b408fb69b7887be2c422f48ce7e">More...</a><br/></td></tr>
<tr class="separator:abd978b408fb69b7887be2c422f48ce7e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aebae4bdcd3930372d639b85c5c9301e8"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">APR</a> [4]</td></tr>
<tr class="memdesc:aebae4bdcd3930372d639b85c5c9301e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0D0 (R/W) Active Priority Register.  <a href="#aebae4bdcd3930372d639b85c5c9301e8">More...</a><br/></td></tr>
<tr class="separator:aebae4bdcd3930372d639b85c5c9301e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ade3473ace2a8bf7c79a0251457be20f4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4">NSAPR</a> [4]</td></tr>
<tr class="memdesc:ade3473ace2a8bf7c79a0251457be20f4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0E0 (R/W) Non-secure Active Priority Register.  <a href="#ade3473ace2a8bf7c79a0251457be20f4">More...</a><br/></td></tr>
<tr class="separator:ade3473ace2a8bf7c79a0251457be20f4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">IIDR</a></td></tr>
<tr class="memdesc:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x0FC (R/ ) CPU Interface Identification Register.  <a href="#aee78d0b6f64a7b47fbd730aabfcc86cf">More...</a><br/></td></tr>
<tr class="separator:aee78d0b6f64a7b47fbd730aabfcc86cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a554bd1f88421df3189c664b9fd9c02aa"><td class="memItemLeft" align="right" valign="top"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">DIR</a></td></tr>
<tr class="memdesc:a554bd1f88421df3189c664b9fd9c02aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset: 0x1000( /W) Deactivate Interrupt Register.  <a href="#a554bd1f88421df3189c664b9fd9c02aa">More...</a><br/></td></tr>
<tr class="separator:a554bd1f88421df3189c664b9fd9c02aa"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<h2 class="groupheader">Field Documentation</h2>
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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::ABPR</td>
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<p>CPU Interface Aliased Binary Point Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829" title="Offset: 0x008 (R/W) Binary Point Register. ">GICInterface_Type::BPR</a> </dd></dl>

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          <td class="memname"><a class="el" href="core__ca_8h.html#a0ea2009ed8fd9ef35b48708280fdb758">__OM</a> uint32_t GICInterface_Type::AEOIR</td>
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<p>CPU Interface Aliased End Of Interrupt Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb" title="Offset: 0x010 ( /W) End Of Interrupt Register. ">GICInterface_Type::EOIR</a> </dd></dl>

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          <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::AHPPIR</td>
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<p>CPU Interface Aliased Highest Priority Pending Interrupt Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6" title="Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register. ">GICInterface_Type::HPPIR</a> </dd></dl>

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          <td class="memname"><a class="el" href="core__ca_8h.html#a4cc1649793116d7c2d8afce7a4ffce43">__IM</a> uint32_t GICInterface_Type::AIAR</td>
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<p>CPU Interface Aliased Interrupt Acknowledge Register </p>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea" title="Offset: 0x00C (R/ ) Interrupt Acknowledge Register. ">GICInterface_Type::IAR</a> </dd></dl>

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          <td class="memname"><a class="el" href="core__ca_8h.html#ab6caba5853a60a17e8e04499b52bf691">__IOM</a> uint32_t GICInterface_Type::APR[4]</td>
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<p>CPU Interface Active Priorities Registers </p>
<dl class="section note"><dt>Note</dt><dd>The register values are IMPLEMENTATION DEFINED. </dd></dl>

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<p>CPU Interface Binary Point Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:3] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[2:0] </td><td align="left">Binary_Point </td><td align="left">Controls how the 8-bit interrupt priority field is split into a group priority field and a subpriority field. </td></tr>
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<p>The binary point (values 0-7) defines the amount of priority bits used as subpriority. Please refer to the section Interrupt prioritization in the <a href="http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ihi0048b/index.html">Arm Generic Interrupt Controller Architecture Specificaton</a> for details. </p>

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<p>CPU Interface Control Register</p>
<p>Enables the signaling of interrupts by the CPU interface to the connected processor, and provides additional top-level control of the CPU interface. In a GICv2 implementation, this includes control of the end of interrupt (EOI) behavior.</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:1] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[0] </td><td align="left">Enable </td><td align="left">Interrupt signaling: 0 - Disable. 1 - Enable. </td></tr>
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<p>CPU Interface Deactivate Interrupt Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The INTID of the interrupt to be disabled. </td></tr>
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<p>CPU Interface End Of Interrupt Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The interrupt number of the finished interrupt. </td></tr>
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<p>CPU Interface Highest Priority Pending Interrupt Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The INTID of the signaled interrupt. </td></tr>
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<p>CPU Interface Interrupt Acknowledge Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:24] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[23:0] </td><td align="left">INTID </td><td align="left">The interrupt number of the signaled interrupt. </td></tr>
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<p>CPU Interface Identification Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:20] </td><td align="left">ProductID </td><td align="left">An IMPLEMENTATION DEFINED product identifier </td></tr>
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<td align="left">[19:16] </td><td align="left">Arch_version </td><td align="left">The version of the GIC architecture that is implemented. </td></tr>
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<td align="left">[15:12] </td><td align="left">Revision </td><td align="left">An IMPLEMENTATION DEFINED revision number for the CPU interface. </td></tr>
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<td align="left">[11:0] </td><td align="left">Implementer </td><td align="left">Contains the JEP106 code of the company that implemented the CPU interface. </td></tr>
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<p>CPU Interface Non-secure Active Priorities Registers </p>
<dl class="section note"><dt>Note</dt><dd>The register values are IMPLEMENTATION DEFINED. </dd></dl>
<dl class="section see"><dt>See Also</dt><dd><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8" title="Offset: 0x0D0 (R/W) Active Priority Register. ">GICInterface_Type::APR</a>[4] </dd></dl>

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<p>CPU Interface Priority Mask Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7:0] </td><td align="left">Priority </td><td align="left">The priority mask level for the CPU interface. </td></tr>
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<dl class="section note"><dt>Note</dt><dd>IMPLEMENTATION DEFINED unsupported priority bits might be RAZ/WI. </dd></dl>

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<p>CPU Interface Running Priority Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:8] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[7:0] </td><td align="left">Priority </td><td align="left">The current running priority on the CPU interface. </td></tr>
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<p>CPU Interface Status Register</p>
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<th align="left">Bits </th><th align="left">Name </th><th align="left">Function  </th></tr>
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<td align="left">[31:5] </td><td align="left">- </td><td align="left">Reserved. </td></tr>
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<td align="left">[4] </td><td align="left">ASV </td><td align="left">Attempted security violation. </td></tr>
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<td align="left">[3] </td><td align="left">WROD </td><td align="left">Write to an RO location. </td></tr>
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<td align="left">[2] </td><td align="left">RWOD </td><td align="left">Read of a WO location. </td></tr>
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<td align="left">[1] </td><td align="left">WRD </td><td align="left">Write to a reserved location. </td></tr>
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<td align="left">[0] </td><td align="left">RRD </td><td align="left">Read of a reserved location. </td></tr>
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